HDL Dynamics is a member of Nexus 5001 Forum Steering Committee supporting the IEEE-ISTO 5001 standards for On-Chip Instrumentation

 see http://www.nexus5001.org/



HDL Dynamics provides consulting and development support on 3 areas of SoC technology

- Patent and Intellectual Property Analysis, addressing both licensing and infringement considerations.

- Development, customization, and migration of on-chip instrumentation IP and soluations.

- Development and creation of customized IP, and migration to new programmable platorms.

HDL Dynamics is focused on solutions to emerging areas in System-on-Chip (SoC) infrastructure and product development. Our key proposition is that emerging complexities in SoC design require understanding and analysis of both both new types of on-chip bulding blocks and IP tools at both systems and silicon levels.

HDL Dynamics has specialized solutions to address:

• In Silicon Analysis and Debug Instrumentation tools
• Performance analysis based optimizations
• Tools and interfaces tying together disconnects between Electronic System (ESL) and on-chip analysis
• Supporting analysis of the underlying patents and Intellectual Properties that are key to effective development of System-on-Chip (SoC) infrastructure and product development



HDL Dynamics provides professional engineering technology and business consulting services in the following areas:

• A full range of on chip instrumentation, analysis, and debug tools
  • Requirements
  • Evaluation,
  • Development,
  • Integration, and
  • Customization
• Digital systems IP and related EDA and SW tools assessment
• Digital Systems IP and related EDA and sw tools Commercialization
• Digital Systems IP Customization and integration
• Integration of ESL and Debug tools and flows

HDL Dynamics have been developing IP Products since 2007. IP is typically developed under a customized basis based on a proven and robust template model.  Available IP Products  include:

• A distributed cross-triggering environment for multicore designs.
• Bus Transactor Blocks for JTAG controlled bus analysis
• Confgurable Bus and SoC level trace solutions                          
• Intelligent Arbitration blocks for improved on chip bus operations - supporting OCP, AMBA, and Core Connect architectures.
• CUstomized conversion of PLD and FPGA blocks. including support for legacy PLD models and lanaguages  such as PALASM and ABEL,